Subject Details
Dept     : CSE
Sem      : 3
Regul    : 2019
Faculty : K.Suriya
phone  : NIL
E-mail  : suriya.k.ece@snsct.org
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Lecture Notes

UNIT 1:
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Number Systems
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Boolean Postulates and laws
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Demorgan’s theorem - Principle of Duality, Boolean expression.
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Minimization of Boolean expression -Minterms and Maxterm, SOP – POS
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Karnaugh Map Minimization
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Don’t Care Conditions
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Tabulation Method
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Logic Gates
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Implementation of Logic functions using Gates
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NAND - NOR Implementation
UNIT 2:
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Carry Look Ahead Adder, Serial Adder/ Subtractor
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Design Procedure - Half Adder - Full Adder
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Half Subtractor - Full Subtractor
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Parallel Binary Adder & Subtractor, Fast Adder
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BCD Adder, Binary Multiplier
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Multiplexer & Demultiplexer, Encoder & Decoder
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Multiplexer & Demultiplexer, Encoder & Decoder
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Parity Checker and Generator
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Code Converters (Binary to Gray, Gray to Binary)
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Magnitude Comparator (2-bit)
UNIT 3:
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Design thinking approach of Edge triggered Flip flops: SR, JK - Characteristic table and equation, Application table
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Latches (SR, Clocked SR)
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Design thinking approach of Edge triggered Flip flops: SR, JK - Characteristic table and equation, Application table
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Edge triggered Flip flops: T, D, Master Slave - Characteristic table and equation, Application table
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Design of synchronous counters
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Up/down counter
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Modulo–n counter
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Decade counters
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Synchronous Counters
UNIT 4:
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Register, Shift registers
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Register, Shift registers
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Universal shift register
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Ring counters
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Design of synchronous sequential circuits: State diagram, State table
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Classification of sequential circuits: Moore and Mealy
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Classification of sequential circuits: Moore and Mealy
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Design of synchronous sequential circuits: State minimization, State assignment
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Introduction to Hazards: Static, Dynamic
UNIT 5:
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Memories: ROM, PROM
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EEPROM, RAM
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Programmable Logic Devices: Programmable Logic Array (PLA)
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Implementation of combinational logic using PROM, PLA, PAL
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Digital logic families: TTL
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ECL and CMOS
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ECL and CMOS