UNIT 1:
Boolean Postulates and laws
Demorgan’s theorem - Principle of Duality, Boolean expression.
Minimization of Boolean expression -Minterms and Maxterm, SOP – POS
Karnaugh Map Minimization
Implementation of Logic functions using Gates
NAND - NOR Implementation
UNIT 2:
Carry Look Ahead Adder, Serial Adder/ Subtractor
Design Procedure - Half Adder - Full Adder
Half Subtractor - Full Subtractor
Parallel Binary Adder & Subtractor, Fast Adder
BCD Adder, Binary Multiplier
Multiplexer & Demultiplexer, Encoder & Decoder
Multiplexer & Demultiplexer, Encoder & Decoder
Parity Checker and Generator
Code Converters (Binary to Gray, Gray to Binary)
Magnitude Comparator (2-bit)
UNIT 3:
Design thinking approach of Edge triggered Flip flops: SR, JK - Characteristic table and equation, Application table
Design thinking approach of Edge triggered Flip flops: SR, JK - Characteristic table and equation, Application table
Edge triggered Flip flops: T, D, Master Slave - Characteristic table and equation, Application table
Design of synchronous counters
UNIT 4:
Register, Shift registers
Register, Shift registers
Design of synchronous sequential circuits: State diagram, State table
Classification of sequential circuits: Moore and Mealy
Classification of sequential circuits: Moore and Mealy
Design of synchronous sequential circuits: State minimization, State assignment
Introduction to Hazards: Static, Dynamic
UNIT 5:
Programmable Logic Devices: Programmable Logic Array (PLA)
Implementation of combinational logic using PROM, PLA, PAL
Digital logic families: TTL