Lecture Notes || SNS Courseware

Subject Details

Dept : ECE

Sem : 5

Regul : 2019

Faculty : Dr. B.Sivasankari

phone : NIL

E-mail : sivasa.b.ece@snsct.org

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Lecture Notes

UNIT 1:

CMOS fabrication- p-well process

n-well process

twin tub process

Non-ideal IV effects

CV characteristics

CMOS inverter –DC characteristics

Stick diagram, Layout diagrams

UNIT 2:

Examples of Combinational Logic Design,

Pass transistor Logic,

Pseudo NMOS logic

static and dynamic CMOS design

Power dissipation

Low power design principles

UNIT 3:

Static and Dynamic Latches and Registers

Timing issues

pipelines

Synchronous design and Asynchronous

clock strategies

Low power memory circuits

UNIT 4:

VLSI testing -need for testing,

manufacturing test principles

Design strategies for test

Design for testability

BIST

CHIP LEVEL TECHNIQUES

SYSTEM LEVEL TECHNIQUES

UNIT 5:

verilog HDL - Intro _ basics

gate primitives, gate delays

verilog HDL -Operators and timing controls

verilog HDL-Procedural assignments ,Conditional statements

verilog HDL- Design hierarchies, Behavioral and RTL modeling

verilog HDL- Test benches,6 examples

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