Subject Details
Dept     : AIML
Sem      : 3
Regul    : 2019
Faculty : E.Ramya
phone  : NIL
E-mail  : ramya1791@gmail.com
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Lecture Notes

UNIT 1:
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Sum of Products (SOP) – Product of Sums (POS)
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Boolean expression
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Number systems
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Boolean postulates and laws
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Logic Gates
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Tabulation method.
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NAND–NOR implementations
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Karnaugh map Minimization
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Don’t Care Conditions
UNIT 2:
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Design Procedure - Half Adder - Full Adder
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Half Subtractor - Full Subtractor
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Parallel Binary Adder & Subtractor, Fast Adder
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Carry Look Ahead Adder, Serial Adder/ Subtractor
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Multiplexer & Demultiplexer, Encoder & Decoder
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Multiplexer & Demultiplexer, Encoder & Decoder
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Multiplexer & Demultiplexer, Encoder & Decoder
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Parity Checker and Generator
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Code Converters (Binary to Gray, Gray to Binary)
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Magnitude Comparator (2-bit)
UNIT 3:
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Latches (SR, Clocked SR)
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Design thinking approach of Edge triggered Flip flops: SR, JK - Characteristic table and equation, Application table
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Synchronous Counters
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Modulo–n counter
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Design and implementation of 3 bit synchronous and asynchronous counters
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Decade counters
UNIT 4:
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Register, Shift registers
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Universal shift register
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Ring counters
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Classification of sequential circuits: Moore and Mealy
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Introduction to Hazards: Static, Dynamic
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Design of synchronous sequential circuits: State minimization, State assignment