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Subject Details

Dept : AIML

Sem : 3

Regul : 2019

Faculty : A.Sakira Parveen

phone : NIL

E-mail : sakiraparveen.a.ece@snsct.org

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Lecture Notes

UNIT 1:

Minimization Techniques : Number Systems.

Karnaugh-Map minimization

Logic Gates : AND,OR,NOT,NAND,NOR,EX-OR, EX-NOR .

Minimization of Boolean expressions – Minterm – Maxterm - SOP – POS.

Demorgan’s theorem-Principle of Duality, Boolean expression.

Don’t Care Conditions.

Tabulation Method.

NAND- NOR Implementation.

UNIT 2:

BCD Adder, Binary Multiplier, Multiplexer.

Parity Checker and Generator.

Demultiplexer, Encoder – Decoder.

BCD Adder, Binary Multiplier, Multiplexer.

Magnitude Comparator.

Parity Checker and Generator.

Parallel Binary Adder, Parallel Binary Subtractor – Fast adder

UNIT 3:

Latches (SR, Clocked SR)

Analysis & Design of Synchronous Sequential Circuit : Synchronous Counters.

Decade counters.

Design thinking approach of Edge triggered Flip flops SR, JK, T, D

Modulo–n counter.

UNIT 4:

Shift registers.

Classification of sequential circuits: Moore and Mealy.

State diagram, State table.

State minimization, State assignment.

Introduction to Hazards: Static, Dynamic.

Ring counters.

Design of synchronous sequential circuits.

Universal shift register.

UNIT 5:

Memories: ROM, PROM.

EEPROM, RAM.

Programmable Logic Devices: Programmable Logic Array (PLA).

Programmable Array Logic (PAL).

Implementation of combinational logic using PROM .

PLA, PAL.

ECL and CMOS.

Digital logic families: TTL.

Implementation of combinational logic using PROM .

Programmable Logic Devices: Programmable Logic Array (PLA).

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