Lecture Notes || SNS Courseware

Subject Details

Dept : ECE

Sem : 5

Regul : 2019

Faculty : m.pradeepa

phone : NIL

E-mail : pradeepa.m.ece@snsct.org

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Lecture Notes

UNIT 1:

CMOS fabrication – p-well process

n-well process

, twin-tub process

MOS transistor theory-IV characteristics

CV characteristics

Non-ideal IV effects

, CMOS inverter –DC characteristics

Stick diagram

, Layout diagrams

, CMOS inverter –DC characteristics

UNIT 2:

Examples of Combinational Logic Design

Pass transistor Logic & Transmission gates

Pseudo NMOS logic

Static CMOS design

Domino Logic

Power dissipation

Low power design principles

UNIT 3:

Static and Dynamic Latches and Registers

Timing issues

Pipelines

Clock strategies

Low power memory circuits

Synchronous design.

UNIT 4:

VLSI test

CHIP LEVEL TEST TECHNIQUES & SYSTEM LEVEL TEST TECHNIQUES.

BIST & BOUNDARY SCAN

Design Strategies

UNIT 5:

Basic Concepts and Identifiers

gate primitives gate delays

operators timing controls

procedural assignments conditional statements

Design hierarchies Behavioral and RTL modeling

Test benches, Examples: decoder, equality detector, comparator, priority encoder, full adder, Ripple carry adder and D flip flop

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