Lecture Notes || SNS Courseware

Subject Details

Dept : ECE

Sem : 5

Regul : 2019

Faculty : Dr.Swamynathan S M

phone : NIL

E-mail : swamyn.m.coe@snsct.org

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Lecture Notes

UNIT 1:

CMOS fabrication – p-well process

n-well process

twin-tub process

MOS transistor theory-IV characteristics

CV characteristics

Non-ideal IV effects

CMOS inverter –DC characteristics

Stick diagram

Layout diagrams

UNIT 2:

Examples of Combinational Logic Design

Pass transistor Logic

Transmission Gates

Pseudo nMOS Logic

Static CMOS Design

Dynamic CMOS Design

Domino Logic

Power Dissipation

Low Power Design Principles

UNIT 3:

Static and Dynamic Latches and Registers

Static and Dynamic Latches and Registers

Timing issues

Pipelines

Clock strategies

Clock strategies

Low power memory circuits

Synchronous design.

Asynchronous design

UNIT 4:

VLSI testing

Need for testing

Manufacturing test principles

Design strategies for test

Design strategies for test

Design For Testability

BIST

Chip level and system level test techniques

Chip level and system level test techniques

UNIT 5:

Basic concepts, identifiers

Gate primitives & gate delays

Operators and timing controls

Procedural assignments conditional statements

Procedural assignments conditional statements

Design hierarchies

Behavioral and RTL modeling, Test benches

Examples: decoder, equality detector, comparator

Ripple carry adder and D flip flop.