Subject Details
Dept     : IT
Sem      : 3
Regul    : 2019
Faculty : P.Uma Maheshwari
phone  : NIL
E-mail  : uma.p.ece@snsct.org
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Lecture Notes

UNIT 1:
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Boolean expression
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Boolean expression
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Implementation of logic functions
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minimization techniques
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Tabulation method
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SOP,POS
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minimization techniques
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Karnaugh map Minimization
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Karnaugh map Minimization
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Logic gates
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Tabulation method
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Logic gates
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Dont care terms
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Tabulation method
UNIT 2:
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Half subtractor
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Design of half adder and full adder
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Full subtractor
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De-Multiplier
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Decoder-Encoder
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Magnitude Comparator
UNIT 3:
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Flipflops
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Flipflops-JK,T,D
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Flipflops-JK,T,D
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Latches
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Edge trigger-Master and Slave
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Design of Synchronous counters
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Modulo-N
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Decade counters
UNIT 4:
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Resister
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Shift register
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Universal Shift register
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Ring counters
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classification of sequential circuits: Moore and Mealy
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classification of sequential circuits: Moore and Mealy
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classification of sequential circuits: Moore and Mealy
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state diagram, state table
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state minimization, state assignment
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Introduction to Hazards: static and dynamic
UNIT 5:
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Memories:ROM,PRAM
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EEROM,RAM
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PLA
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PLA
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PLA
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Digital Logic Families :TTL
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ECL,CMOS
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ECL,CMOS
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Simulation of combinational circuits
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Simulation of Sequential Circuits