Subject Details
Dept     : CSE
Sem      : 3
Regul    : 2019
Faculty : H.Umamaheswari
phone  : NIL
E-mail  : uma.h.ece@snsct.org
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Lecture Notes

UNIT 1:
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Number systems
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Boolean Expression,Minimization of boolean expressions
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Minterms-Maxterms-Sum of Products(SOP)-Product of Sums(POS)
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Tabulation method
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Logic Gates : AND,OR,NOT,NAND,NOR,EXOR,EXNOR-Implementation of logic functions using Gates
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NAND-NOR Implementation
UNIT 2:
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Half Adder,Full Adder
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Parallel Binary Adder,Subtractor.
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Parity Checker and Generator.
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Code Converters (Binary to Gray, Gray to Binary).
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BCD Adder,Binary Multiplier, Multiplexer.
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Carry Look Ahead Adder,Serial Adder/Subtractor
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Demultiplexer , Encoder – Decoder
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Demultiplexer , Encoder – Decoder
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Magnitude Comparator ( 2 Bit).
UNIT 3:
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Latches (SR, Clocked SR)
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Design thinking approach of Edge triggered Flip flops SR, JK, T, D
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Master slave – Characteristic table and equation.
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Design of synchronous counters.
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Modulo–n counter.
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Modulo–n counter.
UNIT 4:
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Shift registers.
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Ring counters.
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Classification of sequential circuits: Moore and Mealy.
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Design of synchronous sequential circuits.
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Design of synchronous sequential circuits.
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Introduction to Hazards: Static, Dynamic.
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Classification of sequential circuits: Moore and Mealy.
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Classification of sequential circuits: Moore and Mealy.
UNIT 5:
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Memories: ROM, PROM,EPROM,EEPROM,RAM
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Digital Logic Families,TTL
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Implementation of PLD
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ECL
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Digital Logic Families CMOS
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Memories: ROM, PROM,EPROM,EEPROM,RAM
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Memories: ROM, PROM,EPROM,EEPROM,RAM