Subject Details
Dept     : ECE
Sem      : 5
Regul    : r 2019
Faculty : Mr.J.Prabakaran
phone  : 9551144859
E-mail  : prabakaran.j.ece@snsct.org
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  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:
    CMOS fabrication- p-well process,
    n-well process,
    Twin-tub process,
    MOS transistor theory , IV characteristics,,
    Non-ideal IV effects,
    CMOS inverter –DC characteristics,
    CV characteristics,
    Stick diagram,
    Examples of Combinational Logic Design,
    Pass transistor Logic & Transmission gates,
    Pseudo NMOS logic,
    Static CMOS design,
    Power dissipation,
    Low power design principles,
    Static and Dynamic Latches and Registers,
    Timing issues,
    Pipelines,
    Clock strategies,
    Low power memory circuits,
    Synchronous design.,
    VLSI testing,
    Manufacturing test principles,
    Design strategies for test,
    BIST,
    Chip level and system level test techniques,
    Basic concepts, identifiers-,
    Gate primitives & gate delays,
    Operators and timing controls,
    Procedural assignments conditional statements,
    Design hierarchies,
    Test benche Examples: decoder, equality detector, comparator

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:
    CMOS fabrication- p-well process,
    n-well process,
    Twin-tub process,
    MOS transistor theory , IV characteristics,,
    Non-ideal IV effects,
    CV characteristics,
    CMOS inverter –DC characteristics,
    Stick diagram,
    Layout diagrams,
    Examples of Combinational Logic Design,
    Pass transistor Logic & Transmission gates,
    Pseudo NMOS logic,
    Static CMOS design,
    Power dissipation,
    Low power design principles,
    Static and Dynamic Latches and Registers,
    Timing issues,
    Clock strategies,
    Pipelines,
    Synchronous design.,
    Low power memory circuits,
    VLSI testing,
    Manufacturing test principles,
    Design strategies for test,
    Chip level and system level test techniques,
    BIST,
    Basic concepts, identifiers-,
    Gate primitives & gate delays,
    Operators and timing controls,
    Procedural assignments conditional statements,
    Design hierarchies,
    Behavioral and RTL modeling, Test benche

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