Subject Details
Dept     : ECE
Sem      : 7
Regul    : 2013
Faculty : K.Sangeetha
phone  : NIL
E-mail  : sangeethak.ece.snsce@gmail.com
384
Page views
63
Files
9
Videos
7
R.Links

Icon
Syllabus

UNIT
1
FUNDAMENTALS OF COMPUTER DESIGN

Review of Fundamentals of CPU, Memory and IO – Trends in technology, power, energy and cost, Dependability - Performance Evaluation

UNIT
2
INSTRUCTION LEVEL PARALLELISM

ILP concepts – Pipelining overview - Compiler Techniques for Exposing ILP – Dynamic Branch Prediction – Dynamic Scheduling – Multiple instruction Issue – Hardware Based Speculation – Static scheduling - Multi-threading - Limitations of ILP – Case Studies.

UNIT
3
DATA-LEVEL PARALLELISM

Vector architecture – SIMD extensions – Graphics Processing units – Loop level parallelism.

UNIT
4
THREAD LEVEL PARALLELISM

Symmetric and Distributed Shared Memory Architectures – Performance Issues –Synchronization – Models of Memory Consistency – Case studies: Intel i7 Processor, SMT & CMP Processors

UNIT
5
MEMORY AND I/O

Cache Performance – Reducing Cache Miss Penalty and Miss Rate – Reducing Hit Time – Main Memory and Performance – Memory Technology. Types of Storage Devices – Buses – RAID – Reliability, Availability and Dependability – I/O Performance Measures.

Reference Book:

1. Kai Hwang and Faye Briggs, “Computer Architecture and Parallel Processing”, Mc Graw-Hill International Edition, 2000. 2. Sima D, Fountain T and Kacsuk P, ”Advanced Computer Architectures: A Design Space Approach”, Addison Wesley, 2000.

Text Book:

1. John L Hennessey and David A Patterson, “Computer Architecture A Quantitative Approach”, Morgan Kaufmann/ Elsevier, Fifth Edition, 2012.

 

Print    Download